The invention relates generally to integrated circuits and, in particular, to structures for a field-effect transistor and methods of forming a structure for a field-effect transistor.
Complementary-metal-oxide-semiconductor processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct logic gates and as active components in other types of circuits, such as switches used in radiofrequency circuits. Field-effect transistors generally include a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in a channel region between the source and drain to produce a device output current.
A semiconductor-on-insulator substrate permits device operation at significantly higher speeds with improved electrical isolation and reduced electrical losses in comparison with field-effect transistors built using a bulk silicon wafer. Contingent on the thickness of a device layer of the semiconductor-on-insulator substrate, a field-effect transistor may operate in a fully-depleted mode in which a depletion layer in the channel region extends fully to a buried oxide layer of the semiconductor-on-insulator substrate when typical control voltages are applied to the gate electrode.
Silicide may be formed on the source, drain and gate electrode of a field-effect transistor to reduce the contact resistance. Before silicidation, a silicide-blocking layer composed of a dielectric material, such as silicon nitride, is deposited and patterned to open areas to be silicided. The patterning of the silicide-blocking layer may form additional sidewall spacers on the gate electrodes as an artifact. After silicidation, a stress liner may be applied as a conformal layer, and an interlayer dielectric layer may be deposited over the stress liner. As the distance between gate electrodes shrinks, the additional sidewall spacers originating from the patterning of the silicide-blocking layer may prevent the stress liner and/or the interlayer dielectric layer from completely filling the space between adjacent gate electrodes and form a void resulting from pinch-off. During subsequent processing to form contacts, the void may become filled by a metal, such as tungsten, and define a metal subway that can produce contact shorting.
Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.